The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this disclosure and are not admitted to be prior art by inclusion in this section.
Computing and electronic devices include power regulators for stepping battery or external power down to voltages that are suitable for various internal components, such as processors, memory, displays, network interfaces, and the like. Efficiency of power regulation is often an important performance metric because inefficient power regulators produce excessive heat, consume more design space, or reduce run-times of battery-powered devices. To optimize power regulator efficiency, power regulators typically implement multiple operating modes that provide optimal efficiencies over different respective ranges of current loading.
Current loads of many device components (e.g., processors), however, are dynamic and can quickly transition from very low current loads to very high current loads. When these load transitions occur, power regulators often switch between operating modes to accommodate the increased amount of current drawn by the components. In some cases, latency associated with switching between the operating modes allows the increased amount of current to draw down a voltage of the power regulator's output. If the voltage at the regulator's output falls below a minimum specification for the components, the components of the device can be impaired or damaged by operating in a low-voltage condition.